串流列資料連結分析 (SDLA)

訊號頻率的加快以及不斷縮減的振幅，為電腦、通訊及記憶體匯流排測試帶來了挑戰。 Tektronix 的先進串流列資料連結分析解決方案能夠使產品上市前順利完成所需的特性分析、相容性及除錯作業。

SDLA Visualizer for MSO/DPO70000 Series Real Time Oscilloscopes ： SDLA Visualizer 功能包括完整的量測電路解除嵌入、模擬電路嵌入及接收器等化。 SDLA Visualizer 搭配 DPOJET 抖動和眼圖分析可針對電腦、通訊及記憶體匯流排提供全面性的模擬與量測環境。

取樣示波器的 80SJNB 抖動、時序和 SDLA Visualizer 連結分析 ：若將 80SJNB 與 Tektronix DSA8300 取樣示波器搭配使用，使用者便能指定解除嵌入濾波器、時域波形或 S 參數以使用 SDLA Visualizer 通道嵌入和 DFE/FFE 等化。80SJNB 分析軟體也可執行時序與雜訊分析，並取得 3-D 眼圖，對速度達 50GHz 以上的訊號進行深入、精確的評估。
MSO/DPO70000 系列即時示波器的 SignalCorrect™ 軟體與 TCS70902 校驗來源 ：SignalCorrect™ 可使用 TCS70902 快速步驟來源和 MSO/DPO70000 示波器上擷取的響應來執行纜線、治具和其他互連類型的特性分析。根據此特性分析，SignalCorrect 可設計解除嵌入濾波器，以補償互連期間的損耗、提供平坦的響應、進行訊號邊際還原，以藉此提高量測的準確性。

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複雜的串列匯流排連結模型驗證和分析本文重點介紹應用程序框架，使用即時示波器的實際波形來執行串列資料連結建模和分析；接著引入了重新取樣 S 參數的方法，在組合多台儀器時可防止產生假像。
DesignCon 2015 Paper – Hybrid Modeled Measured Characterization of a 320 Gbit/s Backplane System This paper explores a case study of a multilane Ethernet backplane 320 Gbit/s system that is difficult to fully measure and deembed, implements a hybrid method of modeling, deembedding, and …
Correlation of Measurement and Simulation Results using IBIS-AMI Models on Measurement Instruments (DesignCon 2014) Increasing serial bus data rates have resulted in requirements for de-embedding measurement circuits, embedding compliance channels, and applying reference equalizers to open closed data eyes for …
PCI Express Gen5 Automated Multi-Lane Testing Introduction Comprehensive characterization of high-speed links such as PCI Express® require performing measurements of the Transmitter (Tx) and Receiver (Rx) across multiple …
使用 80SJNB 先進軟體進行等化及串列資料連結分析 (SDLA) 方法應用摘要本應用摘要說明易損耗/分散通道上執行的串列資料標準，所使用的測試與量測方法，這類通道使接收器的眼圖閉合，通道中使用等化 (FFE/DFE) 方法來打開眼圖。本應用摘要比較了接收器上進行的量測、示範發射器進行的建議量測，並介紹其他串列資料設計人員與測試設計人員感興趣的 SDLA 概念。
Serial Data Link Analysis SDLA Visualizer software provides extensive capability for computing embed and de-embed filters for real-time measurement and simulation. This application note focuses on the embed and de-embed …

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DDR5 Memory Characterization While they promise to provide datacenters with large amounts of data at faster speeds and lower power consumption, DDR5 memory devices have unique test challenges. Learn about characterization and …
PCIe Gen5 Rx Calibration Listen as Joey Chiu, Tektronix PCI Express Applications Engineer, discusses PCI Express Gen5 Receiver (Rx) calibration. He covers how to prepare for it, what to expect, troubleshooting, and how to …
Using SDLA Visualizer Learn how to open closed eyes using equalization techniques and how to de-embed reflections and loss caused by the measurement setup using SDLA Visualizer for Tektronix Real-Time Oscilloscopes.
TDR Analysis for S Parameter Creation This webinar reviews TDR basics and the ability to create S-parameters using TDR/TDT measurements to validate high speed channels for debug or de-embedding in a Serial Data Link Analysis application.
PCI Express Gen 4 and Gen 5 Transmitter and Receiver Validation PCI Express I/O bandwidth has doubled every 3 years on average thereby leading to an increased demand for this full duplex high speed bus architecture. As the industry begins deploying the 5.0 …
How to Address Your Toughest Serial Bus Design Challenges with EDA and Measurement Correlation This Tektronix webinar will teach engineers how to use modeling tools to correlate simulations with high-speed physical layer measurements on Serial Bus Standards using the DPO/MSO70000 Series …
Advanced Jitter and Noise Analysis As serial data speeds increase, the need to perform accurate timing and jitter measurements is key to staying current in your design role. Check out this new webinar that covers advances in the …