Serial Data Link Analysis (SDLA)

Acceleration of signaling frequencies and shrinking amplitude create challenges for testing Computer, Communications and Memory busses. Tektronix' advanced Serial Data Link Analysis solutions enable a seamless transition between characterization, compliance, and debug tasks required to bring your product to market.

SDLA Visualizer for MSO/DPO70000 Series Real Time Oscilloscopes: the SDLA Visualizer enables complete measurement circuit de-embed, simulation circuit embed and receiver equalization. The SDLA Visualizer with DPOJET Jitter and Eye Analysis provide a comprehensive simulation and measurement environment for Computer, Communications and Memory buses.

80SJNB Jitter, Timing, and SDLA Visualizer Link Analysis for Sampling Oscilloscopes: When used with the Tektronix DSA8300 Sampling Oscilloscope, 80SJNB allows the user to specify a de-embed filter, Time Domain Waveform or S-Parameter for channel embedding using SDLA Visualizer and DFE/FFE Equalization. 80SJNB analysis software also performs timing and noise-based analysis to get a 3-D view of the eye diagram performance for deep, accurate evaluation on signals with speeds beyond 50GHz.
SignalCorrect™ Software and TCS70902 Calibration Source for MSO/DPO70000 Series Real Time Oscilloscopes: SignalCorrect™ allows quick characterization of cables, fixtures and other types of interconnects using the TCS70902 Fast step source and the captured response on a MSO/DPO70000 scope. Based on this characterization, SignalCorrect can design a de-embed filter that compensates for the losses that occur in the interconnects, and offers a flat response, enabling signal margin recovery, leading to more accurate measurements.

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Validation & Analysis of Complex Serial Bus Link Models (DesignCon 2013) This paper highlights an application framework for performing serial data link modeling and analysis using live waveforms on a real-time oscilloscope. It then introduces a method for re-sampling S …
DesignCon 2015 Paper – Hybrid Modeled Measured Characterization of a 320 Gbit/s Backplane System This paper explores a case study of a multilane Ethernet backplane 320 Gbit/s system that is difficult to fully measure and deembed, implements a hybrid method of modeling, deembedding, and …
Correlation of Measurement and Simulation Results using IBIS-AMI Models on Measurement Instruments (DesignCon 2014) Introduction Increasing data rates have resulted in the requirement for post processing of data before measurements can be taken. This post processing typically involves de-embedding …
PCI Express Gen5 Automated Multi-Lane Testing Introduction Comprehensive characterization of high-speed links such as PCI Express® require performing measurements of the Transmitter (Tx) and Receiver (Rx) across multiple …
Equalization and Serial Data Link Analysis Methods (SDLA) with 80SJNB Advanced Application Note This application note describes test and measurement methodology used by serial data standards running on lossy/dispersive channels which close the eye diagram at the receiver, and where equalization …
Serial Data Link Analysis SDLA Visualizer software provides extensive capability for computing embed and de-embed filters for real-time measurement and simulation. This application note focuses on the embed and de-embed …

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DDR5 Memory Characterization While they promise to provide datacenters with large amounts of data at faster speeds and lower power consumption, DDR5 memory devices have unique test challenges. Learn about characterization and …
PCIe Gen5 Rx Calibration Listen as Joey Chiu, Tektronix PCI Express Applications Engineer, discusses PCI Express Gen5 Receiver (Rx) calibration. He covers how to prepare for it, what to expect, troubleshooting, and how to …
Using SDLA Visualizer Learn how to open closed eyes using equalization techniques and how to de-embed reflections and loss caused by the measurement setup using SDLA Visualizer for Tektronix Real-Time Oscilloscopes.
TDR Analysis for S Parameter Creation This webinar reviews TDR basics and the ability to create S-parameters using TDR/TDT measurements to validate high speed channels for debug or de-embedding in a Serial Data Link Analysis application.
PCI Express Gen 4 and Gen 5 Transmitter and Receiver Validation PCI Express I/O bandwidth has doubled every 3 years on average thereby leading to an increased demand for this full duplex high speed bus architecture. As the industry begins deploying the 5.0 …
How to Address Your Toughest Serial Bus Design Challenges with EDA and Measurement Correlation This Tektronix webinar will teach engineers how to use modeling tools to correlate simulations with high-speed physical layer measurements on Serial Bus Standards using the DPO/MSO70000 Series …
Advanced Jitter and Noise Analysis As serial data speeds increase, the need to perform accurate timing and jitter measurements is key to staying current in your design role. Check out this new webinar that covers advances in the …