Measuring MOSFET Gate Charge Using the S530 Parametric Test System

Introduction

Power MOSFETs are often used as high speed switching devices. The switching speed of these devices is affected by internal capacitances that are typically specified in data sheets in terms of C_iss and C_oss, which are derived from the input gate and drain capacitance (C_gs and C_gd). In addition to specifying the capacitance, the gate charge (Q_gs and Q_gd) can also be used to assess the switching performance of the MOSFET.

One method of measuring the gate charge of a MOSFET is described in the JEDEC, JESD24-2 standard, “Gate Charge Test Method”. With this method, a gate current is forced while the gate to source voltage is measured as a function of time. From the resulting gate voltage waveform, the gate-source charge (Q_gs), gate-drain charge (Q_gd), and gate charge (Q_g) are derived.

The S530 Parametric Test System provides support for gate charge testing. On this system, the gate charge application is called from the Keithley Test Environment (KTE) Software. This application note describes how to make these gate charge measurements on a MOSFET based on the JEDEC Gate Charge Test Method using these test systems.

Gate Charge Measurement Overview^*

In the Gate Charge Method, a fixed test current (I_g) is forced into the gate of a MOS transistor and the measured gate source voltage (V_gs) is plotted against the charge flowing into the gate. A fixed voltage bias is applied to the drain terminal. Figure 1 is a graph of the gate voltage vs. gate charge of a power MOSFET.

The gate charge (Q) is derived from the forced gate current and time, (I_gdt). The gate-source charge (Q_gs) is the charge required, as shown in Figure 1, to reach the beginning of the plateau region where the voltage (V_gs) is almost constant. The plateau (or Miller) voltage (V_pl) is defined, according to the JEDEC standard, as the gate-source voltage when dV_gs/dt is at a minimum. The voltage plateau is the region when the transistor is switching from the OFF state to the ON state. The gate charge required to complete this switching, that is the charge needed to switch the device from the beginning of the plateau region to the end, is defined as gate-drain charge (Q_gd) and is known as the Miller charge. The gate charge (Q_g) is the charge from the origin to the point where the gatesource voltage (V_gs) is equal to a specified maximum (V_gsMax).

S1 is the slope of the line segment from the origin to the first plateau point. S2 is the slope of the line segment from the last plateau point to the specified maximum gate voltage (V_gsMax). The slopes are used to calculate Q_gs and Q_gd, as specified in the JESD24-2 standard.

Figure 2 shows typical gate and drain waveforms as a function of time. As current is forced to the gate, V^gs increases until it reaches the threshold voltage. At this point, the drain current (I^d) begins to flow. When C^gs is charged up at time t1, I^d stays constant and the drain voltage (V^d) decreases. V^gs remains constant until it reaches the end of the plateau. Once C^gd is charged at time t2, the gatesource voltage (V^gs) starts to increase again until it reaches the specified maximum gate voltage (V^gsMax).

Using the S530 for Gate Charge Measurements

The S530 measures gate charge of a power MOSFET using two source measure unit (SMU) instruments. Figure 3 illustrates the basic circuit diagram of the gate charge test. The Force HI terminal of one SMU (SMU1) is connected to the gate terminal of the MOSFET and forces the gate current (I_g) and measures the gate-source voltage (V_gs) as a function of time. A second SMU (SMU2) applies a fixed voltage (V_ds) to the drain at a specified current compliance (I_ds). The maximum compliance current of the SMU is 1 A.

During the gate charge test, the gate voltage increases and turns ON the transistor. During this transition in the plateau region, the drain SMU (SMU2) switches from voltage control to the current control mode, because the current exceeds the specified compliance level. The software returns the drain current transients and drain voltage during the transition from the OFF state to the ON state.

The source terminal of the MOSFET is connected to the Force LO terminal of the SMU.

Configuring the KTE Software for Gate Charge Measurements

To locate the gate charge test in the KTE Software, open the KITT (Keithley Interactive Test Tool) utility. From the Libraries menu, select “HVLIB” library. In the HVLIB library, select and click on the “gate_charge” test function. Once the gate_charge module is open, the KITT Parameter Entry table will appear. The input test parameters are entered in the KITT Parameter Entry window as shown in Figure 4.

Input Parameters

The input parameters will vary depending on the device under test. Refer to Table 1 for the descriptions of the input parameters. First, enter the appropriate Pin number that will be connected to the gate SMU (gatePin) and drain SMU (drainPin) of the MOSFET. The source Pin will always be connected to the GND.

The drain voltage (Vds) is the bias voltage applied to the drain, and drainLimitI is the compliance current of the drain SMU. The magnitude of the current forced to the gate by the gate SMU is the gateCurrent (I_g) parameter. The Coffset parameter, which is used for correcting for the offset capacitance, is described in the following paragraphs.

Correcting for Offset Capacitances

Depending on the cabling and connections of the measurement system, the offset capacitance can be in the range of single picoFarads to hundreds of picoFarads. These capacitances can be corrected by executing the gate_charge test with an open circuit, obtaining the offset capacitance, and then entering the offset capacitance in the Actual Value column in the KITT Parameter Entry window. Here’s how to perform these steps:

1. Measure the offset capacitance. Set up the test parameters including the input gate current as though the device was connected to the SMUs. However, increase the VgsMax just for the Ceff measurement. Prior to executing the test, lift the probes or remove the device from the test fixture. Execute the gate-charge test with an open circuit.
2. Obtain the offset capacitance. After the test is executed, the measured offset capacitance of the system is calculated and appears in the Ceff column in the Results window. Ceff is derived from the maximum gate voltage, gate current, and time. Because an open circuit is measured during this step, a Test Status Value of –9 or –12 may appear in the Results window after the test is executed. This is because no device is measured so there is no plateau region. However, the Ceff value is correct and can be entered as the Coffset as the Actual Value.
3. Enter the measured offset capacitance and execute. Enter the measured offset capacitance (Ceff) for Coffset in the KITT Parameter Entry window. By default, Coffset is 0 F. The offset capacitance will be compensated for in subsequent readings.

Once the input parameters have been entered, click Add to add the function to the KITT utility. The screen will update as shown in Figure 5.

Executing the Test

To execute the test, click the Run button on the side of the screen. As the test is executed, the output parameters will be stored in the KITT Results window (Figure 6).

Output Parameters

After the test is completed, several parameters are returned to the Results window. These parameters and their descriptions are listed in Table 2.

Graphing the Results

If results plotting is enabled, the gate charge waveform will appear in the KCAT (Keithley Curve Analysis Tool) window (Figure 7). In this graph, the gate voltage (V_g), drain voltage (V_d), and the drain current (I_d) are plotted as a function of the gate charge. These parameters can also be plotted as a function of time.

Checking the Test Status

Each time the test is executed,s a test status is returned to the KITT Results table. Table 3 lists the returned Test Status Values and their corresponding descriptions and notes.

Conclusion

The S530 Parametric Test System supports making gate charge measurements on transistors. Using two SMUs connected to the gate and drain of the device allows the KTE software to derive gate charge waveforms easily.

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