With faster memory bus read/write cycles, it becomes critical to verify memory bus timing performance. In this session, you'll receive an update on DDR2 & DDR3 Memory Bus Architecture along with JEDEC-recommended testing verification approaches. Examples showing verification tests using Tektronix test solution for DDR will be performed.
お問い合わせ
ダウンロード
マニュアル、データシート、ソフトウェアなどのダウンロード：
フィードバック