Clarius DDR5 DRAM Tx Compliance and Debug Solution

Specifications

DDR5 DRAM Tx tests

The Clarius DDR5 DRAM Tx solution streamlines the compliance testing process for DDR5 systems and devices, empowering you to achieve faster time-to-market with several innovative features.

Experience a user-friendly, step-by-step interface that accelerates test setup. Effortlessly configure key settings like data rate, acquisition parameters, and test limits within a single, intuitive global configuration window. The interface groups tests logically by category (e.g., Tx DQS Jitter, Tx DQ Jitter, Tx DQ Stressed Eye) and allows for individual measurement selection within each group.

Sources and signals

The Clarius DDR5 DRAM Tx application comes with a unique feature to select or deselect the signal. Once the signal is selected in the sources and signals panel, the user can select the signal source connected to the oscilloscope.

User defined acquisition mode

The Clarius DDR5 DRAM Tx application empowers users with granular control over oscilloscope settings through User Defined Acquisition (UDA) mode. This allows customization of scope acquisition parameters like sample rate, bandwidth, record length etc directly within the automation framework. UDA facilitates tailored test setups for specific JEDEC DDR5 compliance needs, streamlining workflows and reducing errors.

UDA's control extends beyond compliance testing. By adjusting acquisition settings on-the-fly during test execution, engineers can gain deeper insights into signal behavior, enabling faster debug and issue resolution.

DCA Training

The Duty Cycle Adjuster (DCA) Training algorithm uses period and duty cycle measurements on the ODD and EVEN cycle of the DRAM clock to determine the DCA optimal mode register settings. This presents a significant advancement in addressing the industry’s critical need to improve signal reliability and performance by reducing duty cycle error and phase mismatch translated jitter.

Pause before acquisition

Gain more control on signal validation and analysis by changing settings/scripts during the test run using Pause before acquisiton.

De-embed filters

Easily de-embed the fixture and cable effects by applying suitable de-embed filters within the DDR5 standard. Apply filter is applicable for all measurements and setting is present in test level setting.

Comprehensive measurements

The Clarius DDR5 DRAM Tx compliance solution adds a long list of JEDEC specific measurements for DDR5 memory standards. It covers Jitter and Stressed Eye measurements as per the JEDEC standards.

Test selection

The Clarius DDR5 DRAM Tx compliance solution test selection panel allows the user to select the various measurements supported by the application.

• Supports 37 measurements of DDR5 DRAM Tx Tests as per DDR5 JEDEC specification:
  • Supports 12 Tx DQS Jitter Tests
  • Supports 13 Tx DQ Jitter Tests
  • Supports 12 Tx DQ Stressed Eye Tests

Configurations

Ease of use measurement configuration to configure measurements by group instead of running through all the 34 measurements.

Results and reporting

The measurement configurations and JEDEC pass/fail limits are automatically applied for the selected measurements based on the memory specification and the selected speed grade. The results report includes DDR measurements statistical data, measurement plots, and the screenshot of the waveforms with the cursors.

When test execution is complete, the application automatically opens the Results panel and displays the summary of test results.

Verification versus debug

The Clarius DDR5 DRAM Tx compliance solution offers a one-stop shop for both ensuring your designs meet DDR5 specifications and efficiently debugging any issues that may arise.

Automated Compliance Testing: Run comprehensive compliance tests with complete confidence. The solution automates the entire process, eliminating manual steps and ensuring consistent, reliable results.

Advanced Debug Capabilities: Should an issue surface during testing, the Clarius DDR5 DRAM Tx compliance solution solution goes beyond simply identifying the failure. It captures and stores worst-case signal waveforms for later in-depth analysis using DPOJET, our powerful advanced Jitter and Timing analysis software. DPOJET offers both generic jitter and timing analysis measurements to address a wide range of debug needs, as well as DDR5-specific measurements to ensure your design adheres to the latest memory standard. With complete control over measurement settings, you can customize each analysis to gain deeper insights into the root cause of failures, accelerating debug cycles.

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