Ihr Team

Test solutions configured to support common frequencies up to 26.5, 40, 50, 67, 70 and 110 GHz based on equipment selection

The test solutions are configured to support common temperatures of -40°C, +100°C, +125°C with room temperature (25°C to 40°C). 

Specifically, the prober TEL P8XL model can reach temperatures as low as -55°C, while the Accretech model is capable of going down to -40°C.

Since wafer testing is a complex service, I will only highlight a few challenges that are top of mind.

First off, the prevalence of heterogeneous solutions, where multiple devices are integrated into a single package, introduces complexities in tracking and managing these components throughout the testing process. This necessitates robust part identification and traceability systems to ensure the integrity of each element.

Secondly, the shift towards 2.5D solutions has significantly increased the interconnect density for a given Integrated Circuits (ICs). For example, the interconnect spacing on an IC could shrink from 0.150 mm to 0.030 mm. That is a 5X decrease on both the X- and Y-axis leading to an interconnect density increase of up to 25X. With such tight spacing and planarity requirements, new probing solutions and methods must be developed and qualified.

Lastly, as the demand for IC solutions expands, so does the demand on wafer testing. To eliminate opportunities for defects caused by handling, the need to eliminate manual handling is paramount.

To enhance traceability in wafer testing, integrating non-volatile memory directly into the IC design (rather than laser scribing human readable unique identifiers) allows for accuracy and ease of tracking. With this in place it is easy to capture wafer lot, wafer number, and row/column information for each IC, contributing to improved part genealogy and tracking throughout the manufacturing process. By leveraging non-volatile memory, the semiconductor industry can fortify its traceability mechanisms, ensuring that IC traceability is maintained beyond the Semiconductor Value Stream.

As the semiconductor industry evolves to incorporate 2.5D solutions, the increased interconnect density on ICs poses a new challenge. Addressing this calls for innovative probing solutions requiring increase collaboration between test providers, wafer test equipment vendors, and probe solutions suppliers. By working together, advanced probing methods that can adeptly manage the tighter spacing and heightened planarity requirements associated with this shift.

The demand for comprehensive automation in wafer testing is a critical avenue for improvement. These systems that can efficiently eliminate human handling steps leading to the reduction in unwanted defects and enhancing overall efficiency in the testing environment.  By combining AI & Machine Learning to the inspection process, screening can be enhanced to improve screening time and effectiveness, addressing challenges associated with human-dependent procedures.

As demand rises, there's a significant opportunity for innovation in overcoming challenges like heterogeneous integration and increased interconnect density. By integrating non-volatile memory, collaborating on probing solutions, and advancing automation, the future of wafer testing looks promising. As an organization that differentiates themselves by providing best-in-class test services, it is extremely exciting to be involved in such a pivotal time Semiconductor Value Stream.

Wafer probing is commonly used in the semiconductor industry for a variety of applications, including process control, device characterization, failure analysis, and reliability testing.

There are several types of wafer probes, including manual probes, semi-automatic probes, and fully automatic probes. Manual probes require an operator to manually move the wafer to each test site, while semi-automatic and fully automatic probes can automatically move the wafer to each test site.

When selecting a wafer probe, it is important to consider factors such as probe tip size and shape, probe tip material, probe planarity, and probe placement accuracy. Other factors to consider include the number of probes, the size of the wafer, and the required throughput.