PCI Express 3.0 PLL Test MOI for Add-In Cards

This document covers the Method of Implementation (MOI) for PCI Express 3.0 Phase-Lock-Loop (PLL) testing for Add-In Cards (AIC) using BERTScope CR125A, CR175A, or CR286A Clock Recovery instruments with Option PCIE (for Gen 1 or Gen 2 applications) or Option PCIE8G (for Gen 1, Gen 2, or Gen 3 applications).